Title :
Pipeline synthesis of SRSL circuits
Author :
Oreifej, Rashad ; Alsharqawi, Abdelhalim ; Ejnioui, A.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Central Florida, Orlando, FL
Abstract :
In this paper, a methodology to synthesize SRSL pipelines has been presented. The synthesis of SRSL pipelines is formulated as an IP problem subject to area and timing constraints for which a heuristic procedure is proposed and applied on six circuits. Experiments reveal that SRSL pipelining is highly suitable for coarse-grain datapaths where these pipelines can yield throughput beyond the 1 GHz mark for large and deep circuits.
Keywords :
combinational circuits; logic design; network synthesis; IP problem; SRSL circuits; coarse-grain datapaths; combinational network; heuristic procedure; pipeline synthesis; self-resetting stage logic circuits; Circuit synthesis; Clocks; Costs; Delay; Design methodology; Gravity; Information technology; Lakes; Network synthesis; Pipeline processing;
Conference_Titel :
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-9972-61-100-1
Electronic_ISBN :
978-9972-61-100-1
DOI :
10.1109/ICECS.2005.4633512
