Title :
An 8-bit 150-MHz CMOS A/D converter
Author :
Wang, Yun-Ti ; Razavi, Behzad
Author_Institution :
Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA
Abstract :
An 8-bit, 5-stage pipelined ADC employs sliding interpolation, reinterpolation, and interleaving with clock edge reassignment. Fabricated in a 0.6-μm CMOS technology, the ADC achieves a DNL of 0.62 LSB, INL of 1.24 LSB, and SNDR of 43.7 dB at 150 MHz sampling rate. The converter draws 395 mW from a 3.3-V supply and occupies an area of 1.2×1.5 mm2
Keywords :
CMOS integrated circuits; analogue-digital conversion; interpolation; pipeline processing; 0.6 micron; 150 MHz; 3.3 V; 395 mW; 43.7 dB; 8 bit; CMOS A/D converter; clock edge reassignment; five-stage pipeline; interleaving; pipelined ADC; reinterpolation; sliding interpolation; Analog-digital conversion; CMOS technology; Circuits; Clocks; Interleaved codes; Interpolation; Multiplexing; Pipeline processing; Preamplifiers; Sampling methods;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777255
