Getting started with VHDL

This paper describes a module developed by the author for the initial teaching of VHDL. A `self-teach´ approach is adopted whereby students with a minimum of tutor support can progress from a basic knowledge of digital logic to modelling an ALU in six three hour sessions. The course script and its accompanying assessment manual are written in such a way as to be portable and easily updated. Evaluation following three successful years of delivery has shown that this introduction provides a sound basis for more advanced work. Copies of the script and the supporting source code can be obtained from the author