New experimental methodology to extract compact layout rules for latchup prevention in bulk CMOS IC´s

Author

Ker, Ming-Dou ; Lo, Wen-Yu ; Wu, Chung-Yu

Author_Institution

Dept. of IC Product Eng., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

1999

fDate

1999

Firstpage

143

Lastpage

146

Abstract

A new experimental methodology to find the compact layout rules on guard rings is proposed to increase latchup immunity of bulk CMOS ICs. The layout rules are extracted from the experimental test chips with latchup sensors and different drawing spacings. A new latchup prevention design with additional internal guard rings between the I/O cells and the internal circuits is first investigated in the fabricated experimental test chips. Through detailed experimental verification, including the temperature effect, one set of compact layout rules has been established to save the chip size of the pad-limited CMOS IC´s but still with enough latchup immunity in a 0.5-μm bulk CMOS technology

Keywords

CMOS integrated circuits; ULSI; integrated circuit layout; integrated circuit reliability; integrated circuit testing; isolation technology; 0.5 micron; bulk CMOS IC; compact layout rules extraction; experimental methodology; guard rings; high pin count ICs; latchup immunity; latchup prevention; latchup sensors; pad-limited CMOS IC; temperature effect; CMOS integrated circuits; CMOS process; CMOS technology; Circuit testing; Equivalent circuits; Impedance; Integrated circuit layout; Pins; Variable structure systems; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777261

Filename

777261