A next generation architecture optimized for high density system level integration

Author

Cliff, Richard ; Reddy, Srinivas ; McClintock, Cameron ; Jefferson, D. ; Lane, Chris ; Zaveri, Ketan ; Mejia, Manuel ; Lee, Andy ; Ngo, Ninh ; Altaf, Risa ; Pedersen, Bruce ; Heile, Frank ; Schleicher, Jay ; Turner, John

Author_Institution

Altera Corp., San Jose, CA, USA

fYear

1999

fDate

1999

Firstpage

175

Lastpage

178

Abstract

Altera has developed a next generation architecture called APEX ^TM to improve overall logic efficiency, performance and provide a framework to add a much broader range of features which enables complete system level integration of a users system. This new architecture will support a family of devices exceeding 2 million gates in density. Density and speed improvements are achieved through an enhanced hierarchical routing structure

Keywords

circuit optimisation; integrated circuit technology; integrated logic circuits; network routing; programmable logic arrays; APEX^TM; architecture; clock network; density; hierarchical routing structure; high density system level integration; logic efficiency; optimisation; speed; Computer architecture; Integrated circuit interconnections; Integrated circuit technology; Logic devices; Packaging; Programmable logic devices; Routing; Software packages; Technological innovation; Wires;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777268

Filename

777268