A field programmable system chip which combines FPGA and ASIC circuitry

Author

Andrew, William B. ; Carl, Glenn ; Charath, Ravi K. ; Hoff, James F. ; Modo, Ron ; Nguyen, Hung ; Smith, William ; Rhein, David ; Schulingkamp, Joe ; Spivak, Carolyn W. ; Steward, James P. ; Subramaniam, Akila

Author_Institution

Microelectron. Group, Lucent Technol., Allentown, PA, USA

fYear

1999

fDate

1999

Firstpage

183

Lastpage

186

Abstract

The industry´s first combination of FPGA and ASIC technologies is discussed in this paper. This chip known as Field Programmable System Chip (FPSC), combines a regular array of SRAM based FPGA programmable function units (PFUs) and an ASIC area in which any ASIC application which fits the usable area can be implemented. An interface block allows the transfer of data and clocks between the two circuit types. An additional feature is the ability to “program” the ASIC area using RAM bits in the FPGA bit stream that are set aside for this purpose providing the user added flexibility. This paper will describe the OR3TP12, an FPGA device with embedded 66 MHz/64 bits PCI core. A circuit allowing the user to program the FPGA through the PCI interface is also discussed

Keywords

SRAM chips; application specific integrated circuits; field programmable gate arrays; integrated circuit design; logic design; 66 MHz; ASIC circuitry; FPGA; FPSC; OR3TP12; PCI core; PCI interface; RAM bits; SRAM; field programmable system chip; interface block; regular array; Application specific integrated circuits; Field programmable gate arrays; Logic arrays; Logic devices; Logic gates; Microelectronics; Programmable logic arrays; Programmable logic devices; Random access memory; Silicon;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777270

Filename

777270