DocumentCode :
2951857
Title :
FSK zero-crossing demodulator for 802.15.4 low-cost receivers
Author :
Dehaese, N. ; Bourdel, S. ; Barthelemy, H. ; Bachelet, Y. ; Bas, G.
Author_Institution :
L2MP UMR CNRS 6137 Polytech´´Marseille, IMT Technopole de Chateau Gombert, Marseille
fYear :
2005
fDate :
11-14 Dec. 2005
Firstpage :
1
Lastpage :
4
Abstract :
This paper presents an asynchronous binary-FSK demodulator (AZCD) for 802.15.4 (ZigBee) low-cost receivers. Based on the zero-crossing demodulator (ZCD) principle, the proposed demodulator architecture is asynchronous, e.g operating without symbol synchronization. Compared to the Zero Intermediate Frequency Zero-Crossing Demodulator (ZIFZCD) technique, the AZCD performances, in terms of BER as a function of Eb/N0, are degraded of about 3.5 dB but its complexity is much lower since no recovery timing device is needed and AZCD is mainly built with logic gates. Moreover, AZCD performances (BER) are good enough to fulfil 802.15.4 requirements. Indeed, the use of AZCD involves the design of zero-IF receiver with a noise factor (NF) of about 10 dB, which is achievable in a low-cost CMOS process.
Keywords :
frequency shift keying; personal area networks; 802.15.4 low-cost receivers; BER; ZigBee; asynchronous binary-FSK demodulator; low-cost CMOS process; noise factor; zero intermediate frequency zero-crossing demodulator; Bit error rate; CMOS logic circuits; Degradation; Demodulation; Frequency shift keying; Frequency synchronization; Logic devices; Logic gates; Timing; ZigBee;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronics, Circuits and Systems, 2005. ICECS 2005. 12th IEEE International Conference on
Conference_Location :
Gammarth
Print_ISBN :
978-9972-61-100-1
Electronic_ISBN :
978-9972-61-100-1
Type :
conf
DOI :
10.1109/ICECS.2005.4633534
Filename :
4633534
Link To Document :
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