Self-adjusting multiple-period locked delay line For high-resolution multiphase clock generation

We present a novel delay-locked loop (DLL) based architecture for multiphase clock generation with a time resolution finer than the gate delay. The basic idea consists in locking the delay line to a certain multiple of clock periods that is not fixed a priori, but is self-adjusted depending on process and operating conditions, and working frequency. In such a way, a wide locking range is achieved with a very compact delay cell structure. The circuit has been used to design a new TDC architecture in which a resolution (time-bin size) of about 16 ps is reached using a 0.35 mum CMOS technology. Post-layout simulations show the feasibility of the technique.