Debugging RTL Using Structural Dominance

Register-transfer level (RTL) debug has become a resource-intensive bottleneck in modern very large scale integration computer-aided design flows, consuming as much as 32% of the total verification effort. This paper aims to advance the state-of-the-art in automated RTL debuggers, which return all potential bugs in the RTL, called solutions, along with corresponding corrections. First, an iterative algorithm is presented to compute the dominance relationships between RTL blocks. These relationships are leveraged to discover implied solutions with every new solution, thus significantly reducing the number of formal engine calls. Furthermore, a modern Boolean satisfiability (SAT) solver is tailored to detect debugging nonsolutions, sets of RTL blocks guaranteed to be bug-free, and to imply other nonsolutions using the precomputed RTL dominance relationships. Extensive experiments on industrial designs show a three-fold reduction in the number of SAT calls due to solution implications, coupled with faster SAT run-times due to nonsolution implications, resulting in a 2.63x overall speedup in total SAT solving time, demonstrating the robustness and practicality of the proposed approach.