Title :
Multiple twisted data line techniques for coupling noise reduction in embedded DRAMs
Author :
Min, Dong-Sun ; Langer, Dietrich W.
Author_Institution :
Dept. of Electr. Eng., Pittsburgh Univ., PA, USA
Abstract :
New multiple twisted data line techniques to reduce both bit line (BL) and word line (WL) coupling noises in scaled embedded DRAMs are proposed and analyzed. An improved noise/signal ratio resulting from the application of the proposed techniques is confirmed by soft-error rate measurements on test chips with 256-Mbit and 1-Gbit level integration. At the 256-Mbit level, when the proposed techniques are applied to both the BL and WL structures, we achieved a 64% coupling noise reduction compared to the conventional twisted Bl (TBL) and WL schemes
Keywords :
DRAM chips; cellular arrays; high-speed integrated circuits; integrated circuit design; integrated circuit measurement; integrated circuit noise; 1 Gbit; 256 Mbit; bit line; coupling noise reduction; multiple twisted data line techniques; noise reduction; noise/signal ratio; scaled embedded DRAMs; soft-error rate measurements; test chips; word line; Costs; Noise cancellation; Noise level; Noise measurement; Noise reduction; Random access memory; Semiconductor device measurement; Signal to noise ratio; Testing; Threshold voltage;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777280
