A 1.4 V 60 MHz access, 0.25 μm embedded flash EEPROM

Author

Kataoka, Tomonori ; Fuchigami, Ikuo ; Nishida, Yoichi ; Kimura, Tomoo ; Aruga, Rie ; Okuda, Yasushi ; Michiyama, Junji

Author_Institution

Corp. Semicond. Dev. Div., Matsushita Electr. Ind. Co. Ltd., Fukuoka, Japan

fYear

1999

fDate

1999

Firstpage

243

Lastpage

246

Abstract

A 1.4 V 60 MHz embedded flash EEPROM has been developed using a wordline booster circuit, a current comparing sense amplifier and an interleave architecture. A new word-line booster circuit which consists of a high performance charge pump, a voltage regulator and a voltage switch has supplied a stable voltage to the word-line decoder from the supply voltage of 1.4 V. A clock-synchronized read operation with an interleave architecture has contributed to doubling the maximum operating frequency in the flash EEPROM

Keywords

CMOS memory circuits; flash memories; high-speed integrated circuits; memory architecture; 0.25 micron; 1.4 V; 60 MHz; clock-synchronized read operation; current comparing sense amplifier; embedded flash EEPROM; high performance charge pump; interleave architecture; stable voltage; triple-well CMOS process; voltage regulator; voltage switch; word-line decoder; wordline booster circuit; Charge pumps; Circuits; Clocks; Decoding; EPROM; Low voltage; Microcontrollers; Regulators; Switches; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777283

Filename

777283