A CMOS mixed-signal 100 Mb/s receive architecture for fast Ethernet

Author

Shoval, Ayal ; Shoaei, Omid ; Lee, Kathleen O. ; Leonowich, Robert H.

Author_Institution

Lucent Technol., Allentown, PA, USA

fYear

1999

fDate

1999

Firstpage

253

Lastpage

256

Abstract

A 125 Mbaud quad transceiver for 10/100 fast Ethernet has been designed in a 5 V 0.35 μm digital CMOS process. Power consumption for the device is 3 W. Detailed testing show excellent receiver results with error free performance up to 160 m under worst-case baseline wander and crosstalk conditions. The analog receiver uses digital adaptation circuitry to optimize an automatic gain control circuit with baseline wander correction, an equalizer and a DC offset correction circuit

Keywords

CMOS integrated circuits; automatic gain control; data communication equipment; digital communication; local area networks; mixed analogue-digital integrated circuits; receivers; transceivers; 0.35 micron; 100 Mbit/s; 100Base-TX transceiver; 160 m; 3 W; 5 V; AGC circuit; ASIC; CMOS mixed-signal receive architecture; DC offset correction circuit; analog receiver; automatic gain control circuit; baseline wander correction; digital CMOS process; digital adaptation circuitry; equalizer; error free performance; fast Ethernet; quad transceiver; Circuits; Clocks; Communication cables; Degradation; Equalizers; Ethernet networks; Gain control; Intersymbol interference; Pulse transformers; Transceivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777285

Filename

777285