A real time and power efficient HDTV motion estimation architecture using adder-compressors

This paper presents a high performance and power efficient architecture for motion estimation (ME). For this architecture two algorithms are implemented, a Sub-sampled Diamond Search (SDS) and a Quarter Sub-sampled Diamond Search (QSDS), both with Dynamic Iteration Control (DIC) algorithm. The SDS-DIC and QSDS-DIC algorithms can significantly reduce the number of SAD (Sum of Absolute Difference) calculations enabling the development of an efficient hardware design for the ME. The DIC technique allows that the desired throughput can be achievable with a restriction in the number of iterations, which contributes for the reduction of number of clock cycles for the motion vector calculation. The processing units (PU) of the ME were developed by using efficient 4-2 and 8-2 adder-compressors. The results we present show that by using both the adder compressors in the PU and the DIC technique it is possible to obtain an efficient ME architecture with a higher performance and a reduced power consumption. The implemented architecture was described in VHDL. Synthesis results are presented for TSMC 0.18um CMOS standard cell. The architecture can reach real time for HDTV 1080p with power consumptions lower than 33mW.