Self-aligned contacts for 10nm FDSOI Node: From device to circuit evaluation

Author

Niebojewski, H. ; Le Royer, Cyrille ; Morand, Yves ; Rozeau, O. ; Jaud, M.-A. ; Barnola, S. ; Arvet, C. ; Pradelles, J. ; Bustos, Javier ; Pedini, J.M. ; Dubois, Eric ; Faynot, O.

Author_Institution

STMicroelectron., Crolles, France

fYear

2013

fDate

7-10 Oct. 2013

Firstpage

1

Lastpage

2

Abstract

We propose an original architecture adapted to the 10nm transistor node (pitch 64nm) for FDSOI technology. This structure features self-aligned contacts and a gate capping dielectric layer preventing any short in case of lithographic misalignment of contacts. 2D simulations are carried out to quantify parasitic capacitances. Technological solutions are then proposed to optimize this key parameter. Consequences are evaluated at the device and circuit scale. It is shown that the use of low-k materials, such as airgap spacers, is a solid option to meet the 10nm node specifications.

Keywords

MOSFET; capacitance; circuit simulation; electrical contacts; semiconductor device models; silicon-on-insulator; 2D simulations; FDSOI node; airgap spacers; gate capping dielectric layer; low-k materials; parasitic capacitances; self-aligned contacts; size 10 nm; transistor node; Atmospheric modeling; Capacitance; Couplings; Delays; Logic gates; Materials; Transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE

Conference_Location

Monterey, CA

Type

conf

DOI

10.1109/S3S.2013.6716549

Filename

6716549