Title :
A 1.25 GHz 0.35 μm monolithic CMOS PLL clock generator for data communications
Author :
Sun, Lizhong ; Kwasniewski, Tad
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Abstract :
A 1.25 GHz monolithic CMOS PLL clock synthesis unit was designed for data communications. The monolithic PLL consists of a ring oscillator, divider, phase/frequency detector, charge pump and on-chip loop filter. The voltage controlled oscillator incorporates a quadrature output ring structure with sub-feedback loop embedded to speed up the circuit. The design accommodates process, supply voltage and temperature variations. The PLL has been fabricated in a 0.35 μm CMOS process, occupies an active area of 1 mm2 and consumes 100 mW power at 3.3 V
Keywords :
CMOS integrated circuits; circuit feedback; clocks; data communication equipment; high-speed integrated circuits; mixed analogue-digital integrated circuits; phase locked loops; timing circuits; 0.35 micron; 1.25 GHz; 100 mW; 3.3 V; PLL clock generator; charge pump; clock synthesis unit; data communications; divider; monolithic CMOS clock generator; onchip loop filter; phase/frequency detector; quadrature output ring structure; ring oscillator; sub-feedback loop; voltage controlled oscillator; Charge pumps; Circuit synthesis; Clocks; Data communication; Filters; Frequency conversion; Phase detection; Phase frequency detector; Phase locked loops; Ring oscillators;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777288
