Analog design synthesis performing fast pareto frontier exploration

This paper presents a technique for performing analog design synthesis providing a fast feedback for the designer through a reduced exploration of the pareto frontier. Simulated Annealing is used as the optimization algorithm and piecewise linear functions are used as single-objective cost functions in order to produce a smooth and equal convergence of all measurements to the desired specifications on the multi-objective cost function. After the minimum specifications are met, a single-objective optimization is performed for each objective in order to obtain a non-exhaustive exploration of the pareto frontier. The results are filtered to obtain the pareto solutions and then re-filtered for multiple 3-D graphs in order to aid the designer to select the solution that best fit his objectives. The proposed technique was verified in the synthesis of a folded cascode amplifier and the results showed good performances and good trade-off between processing time and pareto-frontier exploration.