An Improved Algorithm for Frequency Response Analysis of Switching Convertes and its Implementation in Verilog-A

This paper presents an improved algorithm to extract frequency response from schematics of switching converter circuits using time domain simulations. The analytically derived ac models involve averaging and different approximations and thus do not properly reflect the frequency response of the system. The proposed approach enables the generation of accurate frequency response characteristics of any switching converter topology, using detailed transistor level models. Implementation in Verilog-A gives the algorithm, portability to any industry standard analog design tools such as Cadence Virtuoso custom design platform. In this algorithm multiple discrete frequency sinusoids are added to generate a perturbation signal and a variable integration time windows are used to extract the frequency response with minimum simulation time and memory overhead. Advanced features of Verilog-A are used to fully automate the extraction procedure.