A novel energy efficient digital controller for charge sharing successive approximation ADC

Successive approximation analog-to-digital converters are very attractive to power-constrained applications due to the topology inherent energy efficiency. This converter architecture most often relies on digital controller circuit to guide the conversion algorithm, and this controller is reported to have an important impact on the overall power consumption, sometimes demanding roughly half the total energy of a given ADC. Therefore, the design of an efficient controller must be of main concern in an ultra-low power ADC. In this paper we present a novel full-custom controller, based on true single phase clock latch, and provide simulation results. The proposed implementation achieves an extreme power reduction using only 13.4% of the energy of a standard cells implementation. We also propose a figure of merit (FOM) to controllers, and use it to compare our topology to a range of state-of-the art ADCs. According to this FOM, the proposed controller exhibits the smallest amount of energy per processed bit currently reported for SAR ADCs.