Compact matrix inversion architecture using a single processing element

Signal processing and communications algorithms often involve computationally demanding manipulations of large complex valued matrices such as matrix inversion. This paper presents a novel, scalable, and compact matrix inversion architecture for inverting complex valued matrices based on QR-factorization via the squared Givens rotations algorithm. We show that the traditional triangular array architectures employing O(n²) communicating processors can be mapped onto a single processor thus avoiding large area consumption. The architecture is implemented using arithmetic operations with a 16bit fixed-point representation and has good numerical accuracy. The hardware architecture has been implemented in an FPGA clocked at 100 MHz and will be used as a core processor in a real-time Capon beamforming system.