DocumentCode
2952426
Title
A low power and radiation-tolerant FPGA implemented in FD SOI process
Author
Lihua Wu ; Guoquan Zhang ; Yan Zhao ; Xiaowei Han ; Bo Yang ; Jianzhong Li ; Jian Wang ; Jiantou Gao ; Kai Zhao ; Ning Li ; Fang Yu ; Zhongli Liu
fYear
2013
fDate
7-10 Oct. 2013
Firstpage
1
Lastpage
2
Abstract
A 330,000 gate field programmable gate array (FPGA) VS12C fabricated on 0.2μm full-depletion silicon-on-insulator (FD SOI) process is presented and the test results indicate this chip has the lower power and higher tolerance to radiation compared with Xilinx radiation-hardened XQVR300 chip implemented on 0.22μm epitaxial silicon. This paper demonstrates the benefit of the FD SOI technology on low power and radiation-tolerant FPGA circuit design.
Keywords
field programmable gate arrays; integrated circuit design; low-power electronics; radiation hardening (electronics); silicon-on-insulator; FD SOI process; VS12C; Xilinx radiation-hardened XQVR300 chip; epitaxial silicon; field programmable gate array; full-depletion silicon-on-insulator process; low power FPGA circuit design; radiation-tolerant FPGA circuit design; size 0.2 mum; size 0.22 mum; Arrays; Field programmable gate arrays; Logic gates; Routing; Silicon; Silicon-on-insulator; Single event upsets;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013 IEEE
Conference_Location
Monterey, CA
Type
conf
DOI
10.1109/S3S.2013.6716566
Filename
6716566
Link To Document