Low cost platform for evolvable-based boolean synthesis

Author

Bonilla, César Pedraza ; Camargo, Carlos Iván

Author_Institution

Fac. de Ing. de Telecomun., Univ. Santo Tomas - Bogota, Bogota, Colombia

fYear

2011

fDate

23-25 Feb. 2011

Firstpage

1

Lastpage

4

Abstract

Evolutionary algorithms are another option for combinational synthesis because they allow for the generation of hardware structures that cannot be obtained with other techniques. This paper shows a parallel genetic programming (PGP) boolean synthesis implementation based on a low cost cluster of an embedded platform called SIE, based on a 32-bit processor and a Spartan-3 FPGA. Some tasks of the PGP have been accelerated in hardware and results have been compared with an HPC implementation, resulting in speedup values up to approximately 180.

Keywords

Boolean functions; combinational circuits; embedded systems; field programmable gate arrays; genetic algorithms; logic design; microprocessor chips; 32-bit processor; HPC implementation; PGP boolean synthesis implementation; SIE; combinational synthesis; embedded platform; evolutionary algorithms; evolvable-based boolean synthesis; hardware structures; low cost cluster; low cost platform; parallel genetic programming; spartan-3 FPGA; speedup values; Biological cells; Computer architecture; Field programmable gate arrays; Genetics; Hardware; Software; Time factors; Embedded systems; Evolutionary algorithms; boolean synthesis; cluster;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (LASCAS), 2011 IEEE Second Latin American Symposium on

Conference_Location

Bogata

Print_ISBN

978-1-4244-9484-2

Type

conf

DOI

10.1109/LASCAS.2011.5750310

Filename

5750310