Characterization and modeling of clock skew with process variations

Author

Zarkesh-Ha, Payman ; Mule, Tony ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1999

fDate

1999

Firstpage

441

Lastpage

444

Abstract

A new compact model for on-chip clock skew as a function of device, interconnect, and system parameter variations is derived. Unlike previous models that describe qualitative behavior of clock skew components, the new model provides a closed form expression for each clock skew component. An example of clock skew components for a typical design using 0.18 μm CMOS technology is investigated

Keywords

CMOS digital integrated circuits; VLSI; circuit layout CAD; clocks; equivalent circuits; integrated circuit layout; integrated circuit modelling; microprocessor chips; network routing; timing; 0.18 micron; closed form equation; closed form expression; compact model; delay equation; equivalent circuit; interconnect variations; internal wire routing delay; on-chip clock skew; process variations; submicron CMOS; symmetric H-tree structure; system parameter variations; Clocks; Digital systems; Fluctuations; Integrated circuit interconnections; Manufacturing processes; Microelectronics; Planarization; Power system interconnection; Semiconductor device modeling; System-on-a-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777319

Filename

777319