Title :
Mesh-structured on-chip power/ground: design for minimum inductance and characterization for fast R, L extraction
Author :
Sinha, Arani ; Chowdhury, Salim
Author_Institution :
Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA
Abstract :
For high-speed circuits, on-chip inductance can no longer be ignored. This paper deals with inductance in the presence of multilayered meshes used for on-chip power supplies. We have shown ways of designing power/ground (p/g) mesh that reduces inductance. Accurate 3-dimensional inductance extraction problem is intractable for large chips. We have demonstrated the feasibility of using flexible-accuracy empirical formulae for fast determination of inductance. We have reported results obtained from a real chip
Keywords :
VLSI; circuit layout CAD; circuit simulation; inductance; integrated circuit interconnections; integrated circuit layout; integrated circuit modelling; power integrated circuits; 3D inductance extraction problem; fast RL extraction; flexible-accuracy empirical formulae; high-speed circuits; mesh-structured on-chip power/ground; minimum inductance; multilayered meshes; on-chip inductance; on-chip power supplies; skin effect; Conductors; Crosstalk; Delay; Frequency; Impedance; Inductance; Integrated circuit interconnections; Integrated circuit noise; Integrated circuit technology; Power supplies;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777323
