Title :
Switching well noise analysis and minimization strategy for low V th CMOS integrated circuits
Author :
Koyama, Akio ; Tsuge, Masatoshi ; Kudo, Jun Ya ; Aida, Tatsuhiro ; Uchida, Makio
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
An accurate equation and solution to estimate switching well noise in CMOS integrated circuits with low Vth is proposed. The propagation characteristics of the noise are fully analyzed with a distributed parameter model, which enables us to derive a novel design guideline and layout strategy to minimize switching well noise
Keywords :
CMOS logic circuits; SPICE; cellular arrays; circuit optimisation; circuit simulation; integrated circuit layout; integrated circuit modelling; integrated circuit noise; low-power electronics; SPICE; cell array; design guideline; distributed parameter model; gate array structure; layout strategy; low threshold voltage CMOS IC; minimization strategy; noise propagation characteristics; parametric analysis; switching well noise analysis; upper limit function; CMOS integrated circuits; Circuit noise; Guidelines; Integrated circuit noise; Minimization; Semiconductor device modeling; Switches; Switching circuits; Variable structure systems; Voltage;
Conference_Titel :
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-5443-5
DOI :
10.1109/CICC.1999.777325
