An algebraic approach for transistor circuit synthesis

This paper presents an algebraic approach for transistor circuit synthesis. Our approach relies on a graph structure which encodes multiple circuit structural configurations. The proposed procedure implicitly enumerates possible circuit configurations via algebraic transformations in the graph structure, and efficiently finds a minimum solution among them. Experimental results on a benchmark suite targeting standard cell implementations show that the proposed procedure generated smaller transistor circuits than a technology mapping based approach in a comparable runtime.