Title :
PCS layout inductance modeling based on a time domain measurement approach
Author :
López, Toni ; Duerbaum, Thomas ; Tolle, Tobias ; Elferich, Reinhold
Author_Institution :
Dept. of Electron. Modules, Philips Res., Aachen, Germany
Abstract :
This paper presents a time domain measurement method to estimate the parasitic inductance of a Printed Circuit Board (PCB) layout. It is based on a lumped element model. The proposed measurement technique is also used for measuring the Equivalent Series Inductance (ESL) of devices such as low ohmic MOSFETs and high current shunt resistors. The PCB layout of a half bridge circuit is characterised as an application example.
Keywords :
SPICE; inductance measurement; parameter estimation; power MOSFET; printed circuit layout; semiconductor device packaging; time-domain analysis; transients; ESL; PCB; SPICE model; current shunt resistors; equivalent series inductance; half bridge circuit; inductance modeling; lumped element model; ohmic MOSFET; parasitic inductance; printed circuit board layout; time domain measurement approach; transients; transistor package; Circuits; Current measurement; Impedance; Inductance measurement; MOSFETs; Packaging; Resistors; SPICE; Scattering parameters; Time measurement;
Conference_Titel :
Applied Power Electronics Conference and Exposition, 2004. APEC '04. Nineteenth Annual IEEE
Print_ISBN :
0-7803-8269-2
DOI :
10.1109/APEC.2004.1296122
