DocumentCode
2953069
Title
A generic convolutional code Viterbi decoder generator
Author
Zhong, Yan ; Yang, Lin ; Rafie, Manouchehr
Author_Institution
ALTA Group of Cadence Design Syst. Inc., Sunnyvale, CA, USA
fYear
1996
fDate
21-24 Oct 1996
Firstpage
206
Lastpage
209
Abstract
This paper presents a unified branch metric calculation method and a unified path-metric update scheduling algorithm to realize the Viterbi decoding process for decoding rate=1/2 convolutional codes. By using punctuation, the proposed algorithm can be extended to decode convolutional codes of any rate. With consideration of the tradeoffs between performance and hardware cost, one can also select different architectures toward different design objectives by specifying the number of processors being used, which results a fully-parallel, fully-serial, or a parallel-serial mixed architecture
Keywords
Viterbi decoding; convolutional codes; digital signal processing chips; Viterbi decoder generator; branch metric index; convolutional code; fully-parallel architecture; fully-serial architecture; parallel-serial mixed architecture; path-metric update; punctuation; scheduling algorithm; Application specific integrated circuits; Clocks; Convolutional codes; Costs; Decoding; Hardware; Very large scale integration; Viterbi algorithm;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562788
Filename
562788
Link To Document