470 MHz digital filter on delta-sigma modulated signals

This paper describes a digital filter operating on Δ-Σ modulated signals. Using a simple processor core comprising an ALU and multiple registers, controlled by an instruction ROM, this circuit operates at 470 MHz in 0.8 μm CMOS. Novel features include partial carry propagation, which reduces circuit delay to that of a single carry-save adder, but results in inexact quantization. On-chip clocking synchronizes low-speed I/O signals to the internal 470 MHz clock. All-N TSPC and conventional TSPC result in a high clock speed of 470 MHz in a 0.8 μm process