Substrate network modeling for CMOS RF circuit simulation

Author

Tin, Suet Fong ; Mayaram, Kartikeya

Author_Institution

Sch. of Electr. Eng. & Comput. Sci., Washington State Univ., Pullman, WA, USA

fYear

1999

fDate

1999

Firstpage

583

Lastpage

586

Abstract

The effect of the substrate network models for use in small-signal CMOS RF circuit simulation is examined in conjunction with the BSIM3 MOSFET model. Detailed comparisons of the small-signal Y and S parameters have been done with both two-dimensional device simulations and measurement data. These comparisons have been made for different bias conditions and channel lengths. It is shown that a simple, one resistance, substrate network model is accurate for small-signal analyses up to a frequency of 10 GHz in a 0.5 μm CMOS process

Keywords

CMOS analogue integrated circuits; S-parameters; UHF integrated circuits; circuit simulation; field effect MMIC; integrated circuit modelling; substrates; 2D device simulations; BSIM3 MOSFET model; CMOS RF circuit simulation; bias conditions; channel lengths; measurement data; small-signal S-parameters; small-signal Y-parameters; small-signal circuit simulation; substrate network modeling; CMOS process; Capacitance; Circuit simulation; Electrical resistance measurement; Immune system; Integrated circuit modeling; MOSFET circuits; Medical simulation; Radio frequency; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Conference_Location

San Diego, CA

Print_ISBN

0-7803-5443-5

Type

conf

DOI

10.1109/CICC.1999.777349

Filename

777349