DocumentCode
2953186
Title
A low-power direct digital frequency synthesizer architecture for wireless communications
Author
Bellaouar, A. ; Obrecht, M. ; Fahim, A. ; Elmasry, M.I.
Author_Institution
VLSI Res. Group, Waterloo Univ., Ont., Canada
fYear
1999
fDate
1999
Firstpage
593
Lastpage
596
Abstract
A novel low-power direct digital frequency synthesizer (DDFS) architecture is presented. The sine and cosine functions are generated by linearly interpolating between the sample points, reducing the size of the ROM look-up table to 416 bits for 9-bit output resolution. The DDFS is implemented in 0.8 μm CMOS technology and features 60 dBc spectral purity, 48 Hz frequency resolution, with only 9.5 mW (@30 MHz, 3.3 V) power dissipation
Keywords
CMOS digital integrated circuits; application specific integrated circuits; direct digital synthesis; interpolation; low-power electronics; radio equipment; table lookup; 0.8 micron; 3.3 V; 30 MHz; 9.5 mW; ASIC; CMOS technology; ROM lookup table; cosine function; direct digital frequency synthesizer; linear interpolation; low-power DDS architecture; sine function; wireless communications; CMOS technology; Clocks; Frequency synthesizers; Hydrogen; Interpolation; Power dissipation; Read only memory; Table lookup; Very large scale integration; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location
San Diego, CA
Print_ISBN
0-7803-5443-5
Type
conf
DOI
10.1109/CICC.1999.777351
Filename
777351
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