DocumentCode
2953250
Title
A cyclic CMOS time-to-digital converter with deep sub-nanosecond resolution
Author
Chen, Poki ; Liu, Shen-Iuan
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
fYear
1999
fDate
1999
Firstpage
605
Lastpage
608
Abstract
A novel cyclic time-to-digital converter (TDC) is proposed in this paper. The measured resolution (or LSB width equivalent) can reach 68 picoseconds, and the corresponding single-shot errors are around 1/2 LSB width. Under a single 3.3 V power supply, the stand-by current consumption is measured to be 0.3 mA only, including the I/O pads. The operation current consumption is measured to be 370 uA under 100 k/sec measurement rate
Keywords
CMOS integrated circuits; analogue-digital conversion; low-power electronics; 0.3 mA; 3.3 V; 370 muA; 68 ps; cyclic CMOS time-to-digital converter; deep subnanosecond resolution; low-power circuit; single-shot error; stand-by current consumption; Calibration; Circuit testing; Current measurement; Current supplies; Delay lines; Emergency power supplies; Energy consumption; Field programmable gate arrays; Linearity; Power measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999
Conference_Location
San Diego, CA
Print_ISBN
0-7803-5443-5
Type
conf
DOI
10.1109/CICC.1999.777354
Filename
777354
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