An efficient bus architecture for system-on-chip design

This paper presents the issues confronted when integrating system-on-chip (SOC) designs and offers solution through a detailed description of the CoreFrame^TM system-on-chip bus architecture that has dramatically reduced system design and verification effort while enhancing the reusability and customizability of system-on-chip product developments. The CoreFrame on-chip bus architecture is defined along with examples to illustrate how a design friendly bus standard will effect the mix and match of reusable cores without sacrificing performance