Minimizing the effect of the host bus on the performance of a computational RAM logic-in-memory parallel-processing system

This paper describes the system design techniques that have been employed to minimize the effect of the host bus on the performance of a Computational RAM (CRAM) logic-in-memory parallel processing system. Specifically, we describe how the architectural features of the CRAM controller affect instruction execution, utilization of processing elements, time to initialize parallel variables from the host computer, and execution time of scalar operations. Finally, we show that because of the performance-enhancement features of the controller, the transfer characteristics of the host bus has very little effect on the performance of a CRAM system. This means that a CRAM system can be implemented on a wide variety of platforms, including those with slow external buses such as ISA-based computers and embedded systems that use slow microcontrollers