FPGA Implementation of Turbo Product CODEC

Author

Chakraborty, Susmita ; Radhika, T. ; Chakrabarti, Saswat

Author_Institution

G.S.Sanyal Sch. of Telecommun., Inst. of Technol., Kharagpur

fYear

2008

fDate

8-10 Dec. 2008

Firstpage

1

Lastpage

6

Abstract

Error control coding plays a vital role to maintain data accuracy across noisy channel. Turbo product code is a high performance error correcting code. It can be used in any communication system where a significant power saving is required or operating signal to noise ratio is very poor. This paper presents an implementation of a turbo product CODEC with Reed-Muller (16, 5, 8) as constituent codes. The design has been simulated and synthesized successfully in Xilinx Integrated Software Environment.

Keywords

Reed-Muller codes; codecs; error correction codes; field programmable gate arrays; turbo codes; FPGA implementation; Reed-Muller codes; constituent codes; data accuracy; error control coding; error correcting code; noisy channel; turbo product CODEC; Block codes; Codecs; Error correction; Field programmable gate arrays; Iterative algorithms; Iterative decoding; Maximum likelihood decoding; Product codes; Region 10; Testing; Chase algorithm; error control coding; iterative decoding; turbo product code;

fLanguage

English

Publisher

ieee

Conference_Titel

Industrial and Information Systems, 2008. ICIIS 2008. IEEE Region 10 and the Third international Conference on

Conference_Location

Kharagpur

Print_ISBN

978-1-4244-2806-9

Electronic_ISBN

978-1-4244-2806-9

Type

conf

DOI

10.1109/ICIINFS.2008.4798456

Filename

4798456