A high-resolution (< 10 ps RMS) 32-Channel Time-to-Digital Converter (TDC) implemented in a Field Programmable Gate Array (FPGA)

A high-resolution 32-Channel Time-to-Digital Converter (TDC) implemented in a general purpose Field Programmable Gate Array (FPGA) is presented. Dedicated carry chains of the FPGA are utilized for time interpolation purposes inside a clock cycle. A counter running at the system clock frequency provides a global time stamp. These two values, along with the channel number, are then written into a FIFO. An extra effort was performed to improve the resolution beyond the intrinsic cell delay of the carry chain as well as to achieve the same resolution on all 32 channels. Due to large bin width variations a bin-by-bin calibration scheme was used. Time difference measurements between two channels were made to determine the RMS and the time resolution of a single channel. At least 6 ps resolution were achieved for all 32 channels. Additional measurements were performed to characterize the influence of the temperature and voltage variations on the RMS value and the mean. The results of these measurements are also presented in this paper.