Flexible design of SPARC cores: a quantitative study

Author

Bautista, Tomás ; Núñez, Antonio

Author_Institution

Div. of CAD, Univ. of Las Palmas, Spain

fYear

1999

fDate

1999

Firstpage

43

Lastpage

47

Abstract

In this paper we present experimental results obtained during the modelling, design and implementation of a full set of versions of SPARC v8 integer unit core aimed for embedded applications in digital media products. VHDL has been the description language, Synopsis tools those for the logical synthesis, and Duet Technologies´ Epoch has been used for the physical layout of the final circuits. They have been mapped to a 0.35 μm, three metal layers process. The quantitative results given characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions

Keywords

digital arithmetic; hardware description languages; hardware-software codesign; SPARC cores; SPARC v8 integer unit core; VHDL; datapath granularity; design space exploration; logical synthesis; metal layers process; microarchitecture; modelling; quantitative results; quantitative study; Circuit synthesis; Computer architecture; Costs; Design automation; Digital signal processing; Hardware; Microelectronics; Registers; Space technology; Video signal processing;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware/Software Codesign, 1999. (CODES '99) Proceedings of the Seventh International Workshop on

Conference_Location

Rome

ISSN

1092-6100

Print_ISBN

1-58113-132-1

Type

conf

DOI

10.1109/HSC.1999.777389

Filename

777389