Title :
10-ns row cycle DRAM using temporal data storage buffer architecture
Author :
Wakayama, S. ; Gotoh, K. ; Saito, M. ; Araki, H. ; Tsz-Shing Cheung ; Ogawa, J. ; Tamura, H.
Author_Institution :
Fujitsu Labs. Ltd., Kawasaki, Japan
Abstract :
We propose a fast row-cycle DRAM-core architecture, which employs temporal data storage buffers in the sense amplifier and pipelined row-address decoding. The temporal data storage buffers eliminated the restoring time and reduced the bit-line precharge time. The pipelined row-address decoding reduced the skew in its decoding operation. We confirmed a 10 ns row-access cycle time by SPICE simulations based on a 0.24 /spl mu/m DRAM technology.
Keywords :
CMOS memory circuits; DRAM chips; buffer storage; decoding; memory architecture; 0.24 micron; 10 ns; DRAM core architecture; bit-line precharge time reduction; decoding skew reduction; dynamic RAM; fast row-cycle DRAM; pipelined row-address decoding; sense amplifier; temporal data storage buffers; Buffer storage; Circuits; Computer buffers; Decoding; Latches; MOS devices; Random access memory; SPICE; Synthetic aperture sonar; Voltage;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.687987
