A unified formal model of ISA and FSMD

Author

Zhu, Jianwen ; Gajski, Daniel D.

Author_Institution

Dept. of Comput. Eng. & Comput. Sci., California Univ., Irvine, CA, USA

fYear

1999

fDate

1999

Firstpage

121

Lastpage

125

Abstract

In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor architecture and the ASIC architecture. This framework enables the unified treatment of code generation and behavioral synthesis, and is being used in our experimental codesign environment to drive system-on-a-chip synthesis from an object oriented language

Keywords

application specific integrated circuits; finite state machines; formal specification; hardware-software codesign; instruction sets; object-oriented languages; program compilers; ASIC architecture; FSMD; ISA; architectural models; behavioral synthesis; code generation; datapath architecture; experimental codesign environment; finite state machine; formal framework; instruction set architecture; object oriented language; processor architecture; retargetable compilation; system-on-a-chip synthesis; unified formal model; Application specific integrated circuits; Automata; Chip scale packaging; Computer architecture; Computer science; Instruction sets; Object oriented modeling; System performance; System-on-a-chip; Vehicle driving;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware/Software Codesign, 1999. (CODES '99) Proceedings of the Seventh International Workshop on

Conference_Location

Rome

ISSN

1092-6100

Print_ISBN

1-58113-132-1

Type

conf

DOI

10.1109/HSC.1999.777405

Filename

777405