An auto-backgate-controlled MT-CMOS circuit

As various portable systems get popular, the reduction of the power dissipation in LSIs is becoming more essential. The scaling down of both the supply voltage and threshold voltage is effective in reducing the power without a serious degradation of operating speed. The static leakage current, however, enlarges the power in the sleep period when the LSI is not operating. To avoid such undesirable leakage, two methods have been reported recently. One is the multi-threshold (MT) CMOS which utilizes dual threshold voltages for both p- and n-channel transistors. This method, however, requires some means of holding the latched data in the sleep period, which increases the design complexity and the chip area. The other is the variable-threshold (VT) CMOS which controls the backgate bias to increase the threshold voltage of transistors during the sleep period. Although it holds the latched data, it requires a triple-well structure and an additional circuit to control the substrate bias. We propose an auto-backgate-controlled MTCMOS (ABC-MT-CMOS) circuit that holds the latched data in the sleep period with a simple circuit. In this paper, we present the circuit, the layout method and the application of the circuit to a 32-bit RISC microprocessor.