Title :
Network-on-Chip: Challenges for the interconnect and I/O-architecture
Author_Institution :
Integrated Electron. Syst. Lab., Tech. Univ. Darmstadt, Darmstadt, Germany
Abstract :
3D ICs are emerging as a promising solution for scalability, power and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes a number of challenges with respect to cost, technological reliability, thermal budget, integration and so forth. Networks-on-chips (NoCs), which are thoroughly investigated in 2D SoCs design as scalable interconnects, are also well relevant to 3D IC Design. In this paper, special challenges for NoC interconnect architectures design, such as the need for high throughput and/or low latency, high reliability and low power consumption, are presented.
Keywords :
integrated circuit interconnections; network-on-chip; reliability; 2D SoC design; 3D IC design; I/O architecture; NoC interconnect architectures design; input-output architecture; network-on-chip; power consumption; scalable interconnect; Integrated circuit interconnections; Quality of service; Reliability engineering; System performance; System-on-a-chip; Throughput; I/O architectures; Network-on-Chip; on-chip interconnect;
Conference_Titel :
High Performance Computing and Simulation (HPCS), 2012 International Conference on
Conference_Location :
Madrid
Print_ISBN :
978-1-4673-2359-8
DOI :
10.1109/HPCSim.2012.6266920
