Deadlock-free routing algorithms for 3-dimension Networks-on-Chip with reduced vertical channel density topologies

3D ICs have emerged as promising solution for scalability, power consumption and performance demands of next generation Systems-on-Chip (SoCs). Along with the advantages, it also imposes lots of challenges in terms of cost, technological reliability, power, thermal budget and so forth. Networks-on-chip (NoCs), which is thoroughly investigated in 2D SoC design as scalable interconnects, is also well relevant to 3D IC Design. The cost of moving from 2D to 3D for any application should be justified with improvements in performance, power, latency and the utilization of Through-Silicon-Via (TSV). In this paper, we present two generalized routing algorithms for different reduced vertical channel density topologies, which can maintain the performance of the NoC and critically improve the utilization of TSV. The experiments for simulation were done in SystemC-RTL which can achieve more flexibility and maintain the cycle accuracy. From the experimental results in aspects of execution time, average throughput, system interconnect and TSV energy consumption, and TSV utilization, 50% vertical channel density topologies achieved the best trade-off for the given constrains.