3D exploration of software schedules for DSP algorithms

Author

Teich, J. ; Zitzler, E. ; Bhattacharyya, Shuvra S.

Author_Institution

Dept. of Comput. Eng., Paderborn Univ., Germany

fYear

1999

fDate

1999

Firstpage

168

Lastpage

172

Abstract

This paper addresses the problem of exploring tradeoffs between program memory, data memory and execution time requirements (3D) for DSP algorithms specified by data flow graphs. Such an exploration is of utmost importance for being able to analyse the feasibility and range of possible software solutions as part of a hardware/software codesign methodology where the target processor and the code generation style may lead to complete different solutions of the same specification. For solving this multi-objective optimization problem, an Evolutionary Algorithm approach is applied. In particular, a new Pareto-optimization algorithm is introduced. For different well-known target DSP processors, the Pareto-fronts are analyzed and compared

Keywords

data flow graphs; evolutionary computation; hardware-software codesign; DSP algorithms; Pareto-optimization; code generation; data flow graphs; data memory; evolutionary algorithm; execution time requirements; multi-objective optimization; program memory; software schedules; target processor; tradeoffs; Assembly; CD recording; Digital signal processing; Flow graphs; Optimizing compilers; Processor scheduling; Program processors; Scheduling algorithm; Signal processing algorithms; Software algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Hardware/Software Codesign, 1999. (CODES '99) Proceedings of the Seventh International Workshop on

Conference_Location

Rome

ISSN

1092-6100

Print_ISBN

1-58113-132-1

Type

conf

DOI

10.1109/HSC.1999.777426

Filename

777426