• DocumentCode
    2954197
  • Title

    An FPGA implementation of a snoop cache with synchronization for a multiprocessor system-on-chip

  • Author

    Yamawaki, Akira ; Iwane, Masahiko

  • Author_Institution
    Fac. of Eng., Kyushu Inst. of Technol., Kitakyushu
  • Volume
    2
  • fYear
    2007
  • fDate
    5-7 Dec. 2007
  • Firstpage
    1
  • Lastpage
    8
  • Abstract
    FPGA based multiprocessor SoC (MPSoC) is an on-chip multiprocessor with fully programmable feature which can reduce development cost and achieve performance requirement. In order to provide an MPSoC with the low-overhead communication and synchronization methods, this paper attempts to introduce the TSVM (tagged shared variable memory) cache to a snooping cache on the MPSoC. The TSVM cache can improve a performance by combining communication and synchronization with the coherence maintenance. Using an FPGA, we evaluate how extending a conventional snooping cache affects circuitries and clock speed. As a result, the growth of hardware amount and the degradation of clock speed are only 5% and 2% respectively. It is also confirmed that the TSVM cache improves significantly performance and energy efficiency by stalling in synchronization.
  • Keywords
    cache storage; field programmable gate arrays; synchronisation; system-on-chip; FPGA; SoC; clock speed; coherence maintenance; low-overhead communication; multiprocessor system-on-chip; snoop cache; synchronization; tagged shared variable memory cache;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Systems, 2007 International Conference on
  • Conference_Location
    Hsinchu
  • ISSN
    1521-9097
  • Print_ISBN
    978-1-4244-1889-3
  • Electronic_ISBN
    1521-9097
  • Type

    conf

  • DOI
    10.1109/ICPADS.2007.4447729
  • Filename
    4447729