DocumentCode
2954225
Title
A 2 V 900 MHz CMOS phase-locked loop
Author
Jieh-Tsorng Wu ; Mu-Jung Chen ; Cheng-Chung Hsu
Author_Institution
Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan
fYear
1998
fDate
11-13 June 1998
Firstpage
52
Lastpage
53
Abstract
A 2 V 60 mW 900 MHz CMOS phase-locked loop is fabricated using a 0.6 /spl mu/m CMOS technology. The negative-G/sub m/ LC-tuned oscillator employs a variable impedance converter for frequency tuning, and shows a frequency range from 808 MHz to 920 MHz. When phase-locked to an 112.5 MHz reference, the measured phase noise of the 900 MHz output is -96.5 dBc/Hz at 100 kHz offset. Chip size is 2270/spl times/2600 /spl mu/m/sup 2/.
Keywords
CMOS analogue integrated circuits; UHF integrated circuits; circuit tuning; impedance convertors; phase locked loops; phase noise; variable-frequency oscillators; 0.6 micron; 2 V; 60 mW; 808 to 920 MHz; 900 MHz; CMOS PLL; CMOS phase-locked loop; LC-tuned oscillator; frequency tuning; variable impedance converter; CMOS technology; Frequency conversion; Impedance; Noise measurement; Oscillators; Phase locked loops; Phase measurement; Phase noise; Semiconductor device measurement; Tuning;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location
Honolulu, HI, USA
Print_ISBN
0-7803-4766-8
Type
conf
DOI
10.1109/VLSIC.1998.688000
Filename
688000
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