Title :
A compact ring delay line for high speed synchronous DRAM
Author :
Seong-Jin Jang ; Seong-Ho Han ; Chang-Sun Kim ; Young-Hyun Jun ; Hoi-Jun Yoo
Author_Institution :
Design Dept., LG Semicon Co. Ltd., Seoul, South Korea
Abstract :
We proposed a compact delay line scheme, ring delay line (RDL). It has a ring topology instead of linear one. The ring time-to-digital converter (TDC) works with wide range of operating frequencies with the help of a shift register. Since the silicon area of ring TDC is negligible, RDL consumes about half of the other linear delay line´s area. Its locking time is found to be 2 clock cycles and operating current is less than 1 mA.
Keywords :
DRAM chips; delay lines; high-speed integrated circuits; integrated circuit design; clock cycles; compact ring delay line; high speed synchronous DRAM; locking time; operating current; operating frequencies; ring time-to-digital converter; shift register; Clocks; Delay effects; Delay lines; Flip-flops; Propagation delay; SDRAM; Shift registers; Silicon; Space vector pulse width modulation; Topology;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688003
