Title :
An on-chip timing adjuster with sub-100-ps resolution for a high-speed DRAM interface
Author :
Noda, H. ; Aoki, M. ; Tanaka, H. ; Nagahima, O. ; Aoki, H.
Author_Institution :
Semicond. & IC Div., Hitachi Ltd., Tokyo, Japan
Abstract :
A novel fully digital fine-delay generator for a high-speed DRAM interface is proposed. The generator consists of arrayed delay components and generates a group of rail-to-rail delayed signals with sub-100-ps resolution. The input-coupling element (squeezer) in the delay component converges the variations of the resolution. A test device design using 0.35-/spl mu/m technology demonstrates that a resolution of 26 ps can be realized. A timing adjuster using the generator has 2-clock-cycle lock-in time and sub-100-ps error.
Keywords :
CMOS digital integrated circuits; delay circuits; high-speed integrated circuits; integrated circuit design; semiconductor storage; signal generators; timing circuits; arrayed delay components; clock-cycle lock-in time; fully digital fine-delay generator; high-speed DRAM interface; input-coupling element; on-chip timing adjuster; rail-to-rail delayed signals; resolution; squeezer; Circuit testing; Delay effects; Feedback loop; Oscillators; Phased arrays; Propagation delay; Random access memory; Signal generators; Signal resolution; Timing;
Conference_Titel :
VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on
Conference_Location :
Honolulu, HI, USA
Print_ISBN :
0-7803-4766-8
DOI :
10.1109/VLSIC.1998.688004
