Pressure tolerant electronics

This paper is a brief review of progress made toward a usable PTE technology at the Naval Undersea Center, Hawaii. It focuses especially on two of the current problem areas: power transistors and hybrid circuits. Results of COSMOS testing are also included. In earlier tests on plastic encapsulated power transistors a dominant failure mode, cracking of the transistor chip, was identified. Its cause was determined and methods were developed to identify devices subject to this failure mode. Currently, metal hermetic-cased power transistors are being opened and subjected directly to the pressurization liquid. Types tested include single, double, and triple diffused mesas, epitaxials and planars. Three fluids are used: a hydrocarbon oil, Shell Tellus 15; a silicone oil, Dow Coming DC 200-20; and a fluorinert chemical, 3M FC43. Two problems in using hybrid circuitry for pressure tolerant electronics were voids in the substrate-to-header bond and the deformation of the hybrid package. How these problems were solved is covered, as are methods to fill and seal hybrid packages.