5 GByte/s data transfer scheme with bit-to-bit skew control for synchronous DRAM

With the rapid increase of MPU´s operating frequency, faster data transfer is required for memory systems. When the data bus frequency exceeds 100 MHz, controlling flight time variation becomes more crucial. This paper describes a 5 GByte/s data transfer scheme (313 MHz; /spl times/64 bit, double data rate) suitable for synchronous DRAM memory systems. A new multi-output controlled delay circuit of 30 ps resolution eliminates incongruent skew between data traces, and required improvements in the electrical characteristics are illustrated.