DocumentCode
2954753
Title
A 500 MS/s 10-bit CMOS D/A converter
Author
Xiao, Peter ; Shin, John ; Soyuer, Mehmet ; Stawiasz, Kevin
Author_Institution
IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
1996
fDate
21-24 Oct 1996
Firstpage
252
Lastpage
255
Abstract
This paper presents a low-power high-speed 10-bit D/A converter. The chip is implemented in a 0.45-μm ASIC CMOS technology and active chip area is 0.8 mm by 0.4 mm. Its dc DNL (differential nonlinearity) is within 0.53 LSB. The chip dissipates 60 mW at 500 MS/s with 57 dB spur-free dynamic range. The normalized power consumption is only 120 μW/MHz, while achieving the highest sampling rate ever reported for a 10-bit D/A in a CMOS technology
Keywords
CMOS integrated circuits; application specific integrated circuits; digital-analogue conversion; 0.45 micron; 10 bit; 60 mW; ASIC CMOS technology; DC differential nonlinearity; LSB; MSB; active chip area; dynamic range; low-power high-speed D/A converter; power consumption; sampling rate; Application specific integrated circuits; Artificial intelligence; CMOS logic circuits; CMOS technology; Decoding; Dynamic range; Energy consumption; MOS devices; Switches; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC, 1996., 2nd International Conference on
Conference_Location
Shanghai
Print_ISBN
7-5439-0940-5
Type
conf
DOI
10.1109/ICASIC.1996.562800
Filename
562800
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