A delay-locked loop and 90-degree phase shifter for 100 Mbps double data rate memories

Author

Yoshimura, T. ; Nakase, Y. ; Watanabe, N. ; Morooka, Y. ; Matsuda, Y. ; Kumanoya, M. ; Hamano, H.

Author_Institution

ULSI Lab., Mitsubishi Electr. Corp., Itami, Japan

fYear

1998

fDate

11-13 June 1998

Firstpage

66

Lastpage

67

Abstract

Recent high-speed DRAMs adopt the architecture known as DDR (Double Data Rate) in which data are sent out at both rising and falling edges of the system clock. In order to capture the incoming data, the 90-degree phase shifter is used to shift the phase of the system clock to the center of the data period. Conventional 90-degree shifters have been organized from the PLL. In this paper, the 90-degree phase shift is achieved without a PLL. This shifter is also able to reduce the influence of the clock duty error.

Keywords

CMOS memory circuits; DRAM chips; delay lock loops; high-speed integrated circuits; phase shifters; timing; 0.35 micron; 2.5 V; 35 mW; 800 Mbit/s; 90-degree phase shifter; CMOS DRAM; DDR architecture; DLL; clock duty error reduction; delay-locked loop; double data rate memories; dynamic RAM; high-speed DRAMs; lock recovery circuit; Circuits; Clocks; Delay lines; Detectors; Phase detection; Phase locked loops; Phase shifters; Sampling methods; Synchronization; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 1998. Digest of Technical Papers. 1998 Symposium on

Conference_Location

Honolulu, HI, USA

Print_ISBN

0-7803-4766-8

Type

conf

DOI

10.1109/VLSIC.1998.688006

Filename

688006